逻辑类型
Logic Type | 解码器/多路分解器 Decoder/Demultiplexer |
电路数
Number of Circuits | 1 x 2:4 |
输入数
Number of Inputs | 2 |
电源电压Vcc
Voltage - Supply | 5.2mA，5.2mA |
静态电流Iq
Current - Quiescent (Max) | 单电源 Single Supply |
输出高，低电平电流
Current - Output High, Low | 2 V ~ 6 V |
低逻辑电平
Logic Level - Low | The ’HC139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 10 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception |
高逻辑电平
Logic Level - High | HC139器件设计用于高性能内存解码或需要很短的传输延迟时间的数据路由应用。在高性能的存储系统中，这些解码器解码系统的影响降到最低。当利用一个快速的使能电路的高速存储器时，这些解码器和存储器的使能能时间的延迟时间通常小于存储器的典型的存取时间。这意味着，有效的系统的解码器引入的延迟是可以忽略不计的。 专门针对高速 记忆解码器和数据传输系统 宽工作电压范围为2 V至6 V 输出可以驱动多达10个输入通道负载 低功耗，80μA最大ICC 典型TPD =10纳秒 ±4 mA输出驱动，在5 V时 低输入电流1μA最大 合并两个使能输入以便简化 级联和/或接收数据 |
传播延迟时间@Vcc，CL
Max Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 | |