逻辑类型
Logic Type | 多路复用器 Multiplexer |
电路数
Number of Circuits | 4 x 2:1 |
输入数
Number of Inputs | 1 |
电源电压Vcc
Voltage - Supply | 24mA，24mA |
静态电流Iq
Current - Quiescent (Max) | 单电源 Single Supply |
输出高，低电平电流
Current - Output High, Low | 1.2 V ~ 3.6 V |
低逻辑电平
Logic Level - Low | 74LVC157A Quad 2-input multiplexer "The 74LVC157A is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LVC157A. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. It is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common.The device is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S.Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. • 5 V tolerant inputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V • Specified from −40 to 85 °C and −40 to 125 °C." |
高逻辑电平
Logic Level - High | 74LVC157A四路2输入多路复用器 74LVC157A是一个四2输入多路复用器选择四位一个共同的选择输入（S）的控制下，从两个来源的数据。，目前四个输出选择的数据在真正的（非反相）形式。启用输入（E）为低电平有效。当引脚E是高，所有的输出（1Y到4Y）被迫低，无论所有其他的输入条件。两组寄存器的数据移动是一种常见的四种常见的输出总线74LVC157A使用共同的数据的状态的选择（S）输入从该数据来确定的特定的寄存器，它也可以被用来作为函数发生器。 这是非常有用的实施所产生的16个不同的功能与一个变量常见。移动设备的两个变量中的任意4的高度不规则的逻辑是4极，2 - 位上的开关，开关的位置来确定的逻辑执行应用到脚的逻辑电平S.Inputs可驱动无论从3.3 V或5 V设备。此功能允许使用这些设备的翻译在混合3.3 V和5 V应用。 •5 V容限输入与5 V逻辑接口 •宽电源电压范围从1.2 V到3.6 V •CMOS低功耗 •直接接口TTL水平 •符合JEDEC标准： •JESD8-7A（1.65 V至1.95 V） •JESD8-5A（2.3 V到2.7 V） •JESD8-C/JESD36（2.7 V至3.6 V） •ESD保护： HBM JESD22-A114F超过2000 V MM JESD22-A115-B超过200 V CDM JESD22-C101E超过1000 V •指定从-40到85°C和-40至125°C。“ |
传播延迟时间@Vcc，CL
Max Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 | |