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  • Model：74LVC2G74DP
  • Manufacturer：HUABAN
  • Date Code：10NOPB
  • Standard Package：3000
  • Min Order：10
  • Mark/silk print/code/type：V74
  • Package：TSSOP8/SOT505-2

逻辑类型
Logic Type		设置（预设）和复位 Set(Preset) and Reset
电路数
Number of Circuits		D型 D-Type
输入数
Number of Inputs		差分 Differential
电源电压Vcc
Voltage - Supply		1
静态电流Iq
Current - Quiescent (Max)		1
输出高，低电平电流
Current - Output High, Low		200MHz
低逻辑电平
Logic Level - Low		2.5ns
高逻辑电平
Logic Level - High		正边沿 Positive Edge
传播延迟时间@Vcc，CL
Max Propagation Delay @ V, Max CL		32mA，32mA
Description & Applications1.65 V ~ 5.5 V
描述与应用Single D-type flip-flop; positive-edge trigger General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.

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ERIC ELECTRONICS TECHNOLOGY (HK) LIMITED
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74LVC2G74DP
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