最大源漏极电压Vds
Drain-Source Voltage | -25V |
最大栅源极电压Vgs(±)
Gate-Source Voltage | -8V |
最大漏极电流Id
Drain Current | -410mA/-0.41A |
源漏极导通电阻Rds
Drain-Source On-State Resistance | 1.5Ω@ VGS = -2.7V, ID = -250mA |
开启电压Vgs（th）
Gate-Source Threshold Voltage | -0.65~-1.5V |
耗散功率Pd
Power Dissipation | 300mW/0.3W |
| Description & Applications | Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features Very low level gate drive requirements allowing direct operation in 3 V circuits . Compact industry standard SC70-6 surface mount package. |
| 描述与应用 | 双N沟道，数字FET 概述 这些双N沟道逻辑电平增强模式场效应晶体管都采用飞兆半导体专有的，高细胞密度，DMOS技术生产。这非常高密度的过程特别是针对减少通态电阻。该器件设计，尤其是作为一个替代双极数字晶体管和小信号MOSFET的低电压应用。 特点 非常低的水平栅极驱动要求可直接操作3 V电路。 紧凑型工业标准SC70-6表面贴装封装。 |