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74LVC1G19GW Signal Switch, Multiplexer, Decoder SOT-363/SC70-6/TSSOP6 marking VY

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Product description
逻辑类型
Logic Type
解码器/多路复用器 Decoder/Demultiplexer
电路数
Number of Circuits
1 x 1:2
输入数
Number of Inputs
1
电源电压Vcc
Voltage - Supply
32mA,32mA
静态电流Iq
Current - Quiescent (Max)
单电源 Single Supply
输出高,低电平电流
Current - Output High, Low
1.65 V ~ 5.5 V
低逻辑电平
Logic Level - Low
The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW.Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 to +85 °C and −40 to +125 °C.
高逻辑电平
Logic Level - High
74LVC1G19是一个1-2解码器/多路分解器,有着一个共同的输出使能。此器件输入端A上缓冲数据,并当使能(E)输入信号为低,把它传递到输出端1Y(真)和2Y(互补)。在3.3 V或5 V设备下输入可驱动。在混合3.3V和5V的应用程序,允许使用这些设备作为译者。这个装置是完全指定的部分断电应用程序使用IOFF。当断电时,IOFF电路关闭输出,防止破坏回流电流通过设备。 从1.65 V至5.5 V的宽电源电压范围 5 V容限输入与5 V逻辑接口 高抗干扰 符合JEDEC标准: JESD8-7(1.65 V至1.95 V) JESD8-5(2.3 V到2.7 V) JESD8B/JESD36(2.7 V至3.6 V) ESD保护: HBM JESD22-A114F超过2000 V MM JESD22-A115-A超过200 V 24 mA输出驱动器(VCC=3.0 V) CMOS低功耗 闭锁性能超过250 mA 直接接口TTL水平 接受输入电压高达5 V 多种封装选项 指定从-40到+85°C和-40至+125°C。
传播延迟时间@Vcc,CL
Max Propagation Delay @ V, Max CL
Description & Applications
描述与应用
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