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PACDN1404 TVS/ESD 5.5V CPG marking
| 极性 Polarization | 单向 Unidirectional |
| 反向关断电压/工作电压VRWM Reverse Standoff Voltage | 5.5V |
| 反向击穿电压VBR Breakdown Voltage | |
| 峰值脉冲耗散功率PPPM Peak Pulse Power Dissipation | |
| 峰值脉冲电流IPPm Peak Forward Surge Current | |
| 额定耗散功率Pd Power dissipation | |
| Description & Applications | Features • ESD Protection Arrays, Chip Scale Package • 4, 8, or 16 transient voltage suppressors in a single package • In-system Electrostatic Discharge (ESD)protection to 25kV contact discharge per IEC 61000-4-2 international standard • Compact Chip Scale Package (0.65mm pitch) format saves board space and eases layout in space critical applications compared to discrete solutions and traditional wire bonded packages |
| 描述与应用 | 特性 •ESD保护阵列，芯片级封装 •4，8，或16中的瞬态电压抑制器单一封装 •在系统静电放电（ESD）保护25kV的接触放电每IEC61000-4-2国际标准 •紧凑的芯片级封装（0.65mm间距）格式分立式解决方案和传统引线键合封装相比节省了电路板空间，并缓解了空间布局的关键应用 |
