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SN74CBT3125DBQR Signal Switch, Multiplexer, Decoder SSOP-16 marking CU125
| 逻辑类型 Logic Type | FET 总线开关 FET Bus Switch |
| 电路数 Number of Circuits | 1 x 1:1 |
| 输入数 Number of Inputs | 4 |
| 电源电压Vcc Voltage - Supply | |
| 静态电流Iq Current - Quiescent (Max) | 单电源 Single Supply |
| 输出高，低电平电流 Current - Output High, Low | 4.0V ~ 5.5 V |
| 低逻辑电平 Logic Level - Low | The SN74CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Standard ’125-Type Pinout (D, DB, DGV,and PW Packages) 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels |
| 高逻辑电平 Logic Level - High | SN74CBT3125四场效应管总线开关设有独立的线路开关。每个开关被禁用时，相关的输出使能（OE）输入为高。为了确保在开机或断电高阻抗状态，OE应当通过上拉电阻连接到VCC;驱动器的电流吸收能力确定电阻的最小值。 标准'125-型接脚分布（D，DB，DGV，PW包） 5Ω开关连接两个端口之间 TTL兼容的输入电平 |
| 传播延迟时间@Vcc，CL Max Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 |
