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Logic circuit Buffer/Line Driver IDT74LVC125APWR TSSOP14 marking
| 逻辑类型 Logic Type | 非反相 Non-Inverting |
| 电路数 Number of Circuits | 4 |
| 输入数 Number of Inputs | 1 |
| 电源电压Vcc Voltage - Supply | 1.65 V ~ 3.6 V |
| 静态电流Iq Current - Quiescent (Max) | 24mA，24mA |
| 输出高，低电平电流 Current - Output High, Low | This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. |
| 低逻辑电平 Logic Level - Low | 这四总线缓冲门是专为1.65-V至3.6 V的VCC运作。 设有独立的线路驱动器，具有三态输出。 每个输出相关的输出使能（OE）输入为高电平时，被禁用。 |
| 高逻辑电平 Logic Level - High | |
| 传播延迟时间@Vcc，CL Max Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 |
