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Integrated Circuit（IC） NAND gate SN74LVC1G00DRLR SOT-553 marking CAR
| 逻辑类型 Logic Type | 与非门 NAND Gate |
| 电路数 Number of Circuits | 1 |
| 输入数 Number of Inputs | 2 |
| 电源电压Vcc Voltage - Supply | 1.65V~5.5V |
| 静态电流Iq Current - Quiescent (Max) | 10µA |
| 输出高，低电平电流 Current - Output High, Low | -32mA,32mA |
| 低逻辑电平 Logic Level - Low | 0.7 V ~ 0.8 V |
| 高逻辑电平 Logic Level - High | 1.7 V ~ 2 V |
| 传播延迟时间@Vcc，CL Max Propagation Delay @ V, Max CL | 4nS @5v,50pF |
| Description & Applications | SINGLE 2-INPUT POSITIVE-NAND GATE； Available in the Texas Instruments NanoStar™ • Ioff Supports Partial-Power-Down Mode Package Operation • Supports 5-V VCC Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Inputs Accept Voltages to 5.5 V • Max tpd of 3.8 ns at 3.3 V • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) • Low Power Consumption, 10-μA Max ICC – 1000-V Charged-Device Model (C101) • ±24-mA Output Drive at 3.3 V |
| 描述与应用 | 单路2输入正与非门; 可用德州仪器NANOSTAR™•IOFF支持部分掉电模式 包装操作 •支持5-V的VCC操作•闭锁性能超过100 mA每 JESD 78，II类 •接受输入电压为5.5 V •最大TPD为3.8 ns在3.3 V •ESD保护超过JESD22 - 2000-V人体模型（A114-A） •低功耗，10μA最大ICC - 1000-V带电器件模型（C101） •±24 mA输出驱动在3.3 V |
